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| DRAM Austin Semiconductor, Inc. 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY AVAILABLE AS MILITARY SPECIFICATIONS * SMD 5962-90847 * MIL-STD-883 SMJ44400 PIN ASSIGNMENT (Top View) 20-Pin DIP (JD) 20-Pin Flatpack (HR) (400 MIL) DQ1 DQ2 W\ RAS\ A9 A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Vss DQ4 DQ3 CAS\ OE\ A8 A7 A6 A5 A4 FEATURES * Organized 1,048,576 x 4 * Single +5V 10% power supply * Enhanced Page-Mode operation for faster memory access P Higher data bandwidth than conventional page-mode parts P Random Single-Bit Access within a row with a column address * CAS\-Before-RAS\ (CBR) Refresh * Long Refresh period: 1024-cycle Refresh in 16ms (Max) * 3-State unlatched Output * Low Power Dissipation * All Inputs/Outputs and Clocks are TTL Compatible * Processing to MIL-STD-883, Class B available Pin Name A0 - A9 CAS\ DQ1 - DQ4 OE\ RAS\ W\ Vcc Vss Function Address Inputs Column-Address Strobe Data Inputs/Outputs Output Enable Row-Address Strobe Write Enable 5V Supply Ground OPTIONS * Timing 80ns access 100ns access 120ns access * Package(s) Ceramic DIP (400mils) Ceramic Flatpack MARKING -80 -10 -12 The SMJ44400 is offered in a 400-mil, 20-pin ceramic side-brazed dual-in-line package (JD suffix) and a 20-pin ceramic flatpack (HR suffix) that are characterized for operation from -55C to +125C. OPERATION JD HR No. 113 No. 308 Enhanced Page Mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS\ low time and the CAS\ page cycle time used. With minimum CAS\ page cycle time, all 1024 columns specified by column addresses A0 through A9 can be accessed without intervening RAS\ cycles. Unlike conventional page-mode DRAMs, the columnaddress buffers in this device are activated on the * Operating Temperature Ranges M Military (-55oC to +125oC) GENERAL DESCRIPTION The SMJ44400 is a series of 4,194,304-bit dynamic random-access memories (DRAMs), organized as 1,048,576 words of four bits each. This series employs state-of-the-art technology for high performance, reliability, and low-power operation. The SMJ44400 features maximum row access times of 80ns, 100ns, and 120ns. Maximum power dissipation is as low as 360mW operating and 22mW standby. All inputs and outputs, including clocks, are compatible with Series 54 TTL. All addressses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. SMJ44400 Rev. 2.0 10/01 For more products and information please visit our web site at www.austinsemiconductor.com Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 DRAM Austin Semiconductor, Inc. (continued) SMJ44400 Enhanced Paga Mode (continued) falling edge of RAS\. The buffers act as transparent or flowthrough latches while CAS\ is high. The falling edge of CAS\ latches the column addresses. This feature allows the SMJ44400 to operate at a higher data bandwidth then conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when CAS\ goes low. This performance improvement is referred to as enhanced page mode. Valid column address can be presented immediately after row address hold time has been satisfied, usually well in advance of the maximum (access time from column address) has been satisfied. In the event that column addresses for the next cycle are valid at the time CAS\ goes high, access time for the next cycle is determined by the later occurrence of tCAC or tCPA (access time form rising edge of CAS\). Address (A0-A9) Twenty address bits are required to decode 1 of 1,048,576 storage cell locations. Ten row-address bits are set up on inputs A0 through A9 and latched onto the chip by RAS\. The ten column-address bits are set up on pins A0 through A9 and latched onto the chip by CAS\. All addresses must be stable on or before the falling edges of RAS\ and CAS\. RAS\ is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS\ is used as a chip select, activating the output buffer as well as latching the address bits into the column-address buffer. Write Enable (W\) The read or write mode is selected through W\. A logic high on the W\ input selects the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W\ goes low prior to CAS\ (early write), data out reamins in the high-impedance state for the entire cycle permitting a write operation independent of the state of OE\. This permits early-write operation to be completed with OE\ grounded. Data In/Out (DQ1 - DQ4) The high-impedance output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS\ and OE\ are brought low. In a read cycle the output becomes valid after all access times are satisfied. The output remains valid while CAS\ and OE\ are low. CAS\ or OE\ going high returns it to the high-impedance state. SMJ44400 Rev. 2.0 10/01 Output Enable (OE\) OE\ controls the impedance of the output buffers. When OE\ is high, the buffers remain in the high-impedance state. Bringing OE\ low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both RAS\ and CAS\ to be brought low for the output buffers to go into the low-impedance state. Once in the low-ompedance state, they remain in the low-impedance state until either OE\ or CAS\ is brought high. Refresh A refresh operation must be performed at least once every 16ms to retain data. This can be achieved by strobing each of the 1024 rows (A0-A9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS\-only operation can be used by holding CAS\ at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS\-only refresh. Hidden refresh can be performed while maintaining valid data at teh output pin. This is accomplished by holding CAS\ at VIL after a read operation and cycling RAS\ after a specified precharge period, similar to a RAS\-only refresh cycle. The external address is ignored during the hidden refresh cycles. CAS\-before-RAS\ (CBR) and hidden refresh CBR refresh is utilized by bringing CAS\ low earlier than RAS\ (see parameter tCSR) and holding it low after RAS\ falls (see parameter tCSR). For successive CBR refresh cycles, CAS\ can remain low while cycling RAS\. The external address is ignored and the refresh address is generated internally. During CBR refresh cycles the outputs remain in the high-impedance state. Hidden refresh can be performed while maintaining valid data at the output pins. Thsi is accomplished by holding CAS\ at VIL after a read operation. RAS\ is cycled after the specified read cycle parameters are met. Hidden refresh can also be used in conjuction with an early-write cycle. CAS\ is maintained at VIL while RAS\ is cycled, once all the specified early-write parameters are met. Externally generated addresses must be used to specify the location to be accessed during the initial RAS\ cycle of a hidden refresh operation. Subsequent RAS\ cycles (refresh cycles) use the internallygenerated addresses and the external address is ignored. Power Up To achieve proper device operation, an initial pause of 200s followed by a minimum of eight initialization cycles is Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 DRAM Austin Semiconductor, Inc. (continued) SMJ44400 Power Up (continued) required after full Vcc level is achieved. These eight initialization cycles need to include at least one refresh (RAS\-only or CBR) cycle. Test Mode An industry standard Design For Test (DFT) mode is incorporated in the SMJ44400. A CBR with W\ low (WCBR) cycle is used to enter test mode. In the test mode, data is written into and read from eight sections of the array in parallel. All data is written into the array through DQ1. Data is comparted upon reading and if all bits are equal, all DQ pins go high. If any one bit is different, all the DQ pins go low. Any combination read, write, read-write, or page-mode can be used in the test mode. The test mode function reduces test times by enabling the 1M x 4-bit DRAM to be tested as if it were a 512K DRAM where column address 0 is not used. A RAS\-only or CBR refresh cycle is used to exit the DFT mode. LOGIC SYMBOL1 RAM 1024K x 4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 6 7 8 9 11 12 13 14 15 5 20D10/21D0 A 0 1 048 575 RAS\ 4 20D19/21D9 C20[Row] G23/[Refresh Row] 24[Power Down] C21[Column] G24 CAS\ 17 & 23C22 24,25EN 3 W\ 16 OE\ 23,21D G25 DQ1 1 2 DQ2 18 DQ3 19 DQ4 A, 22D 26 A, Z26 1. This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12. The pinouts illustrated are for the JD package. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 DRAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM RAS\ CAS\ W\ OE\ Timeing and Control SMJ44400 A0 A1 Column Address Buffers A9 2 8 Column Decode Sense Amplifiers 128K Array 128K Array R 128K Array 128K Array O W D E C O D E R 128K Array 10 128K Array 16 16 16 Row Address Buffers 16 I/O Buffers 4 of 16 Selection Data In Reg. 4 Data Out Reg. 4 10 2 ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss...............-1V to +7.0V Voltage Range on Any Pin Relative to Vss.........-1V to +7.0V Short Circuit Output Current (per I/O)..........................50mA Power Dissipation.................................................................1W Storage Temperature Range..........................-65C to +150C Operating Temperature Range......................-55C to +125C *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. RECOMMENDED OPERATING CONDITIONS SYM DESCRIPTION MIN 4.5 2.4 -1 -55 125 1 NOM 5 MAX 5.5 6.5 0.8 UNIT V V V C C VCC Supply Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage TA TC Minimum Operating Temperature Maximum Operating Case Temperature 1. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 DRAM Austin Semiconductor, Inc. SYM VOH PARAMETER High-level output voltage TEST CONDITIONS IOH = -5mA IOL = 4.2mA VCC = 5.5V, VI = 0V to 6.5V, All other pins = 0V to VCC VCC = 5.5V, VO = 0V to VCC, CAS\ High VCC = 5.5V, Minimum cycle After 1 memory cycle, RAS\ and CAS\ High, VIH = 2.4V VCC = 5.5V, Minimum cycle, RAS\ cycling, CAS\ High (RAS\ only), RAS\ Low after CAS\ Low (CBR) VCC = 5.5V, tPC = minimum, RAS\ Low, CAS\ cycling SMJ44400 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC VOL Low-level output voltage II IO Input current (leakage) Output current (leakage) ICC1 Read - or write-cycle current1 ICC2 Standby current ICC3 Average refresh current 1 (RAS\ only, or CBR\) 85 75 65 mA ICC4 Average page current2 50 40 35 mA CAPACITANCE (f = 1MHz)3 SYM Ci(A) Ci(RC) Ci(W) CO PARAMETER Input capacitance, address inputs Input capacitance, strobe inputs Input capacitance, write-enable inputs Output capacitance MAX 7 10 10 10 UNIT pF pF pF pF SWITCHING CHARACTERISTICS (-55oC 4 4 -8 MAX 40 20 45 80 20 20 20 -10 MAX 45 25 50 100 25 25 25 -12 MAX 55 30 55 120 30 30 30 UNIT ns ns ns ns ns ns ns NOTES: 1. Measured with a maximum of one address change while RAS\ = VIL. 2. Measured with a maximum of one address change while CAS\ = VIH. 3. VCC = 5V 0.5V and the bias on the pins under test is 0V. Capacitance is sampled only at initial design and after any major change. 4. tOFF and tOEZ are specified when the output is no longer driven. The outputs are disabled by bringing either OE\ or CAS\ High. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 DRAM Austin Semiconductor, Inc. SYM tRC tRWC tPC tPRWC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWSR tCAH tDHR tDH tAR tRAH tRCH tRRH tWCH tWCR tWHR tOEH tROH tAWD tCHR tCRP tCSH tCSR tCWD PARAMETER Cycle time, random read or write Cycle time, read-write Cycle time, page-mode read or write Cycle time, page-mode read-write Pulse duration, page mode, RAS\ low 4 3 3 2 1 SMJ44400 -12 MAX TIMING REQUIREMENTS (-55oC 4 -8 MAX MIN 180 245 60 120 -10 MAX MIN 210 285 65 135 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100000 100 100000 120 100000 10000 10000 100 25 10 70 20 0 0 0 0 25 25 0 10 20 75 20 75 15 0 0 20 75 10 25 25 80 20 0 100 10 60 10000 10000 120 30 15 80 25 0 0 0 0 30 30 0 10 20 90 25 90 15 0 0 25 90 10 30 30 90 25 0 120 10 70 10000 10000 Pulse duration, nonpage mode, RAS\ low Pulse duration, CAS\ low Pulse duration, CAS\ High Pulse duration, RAS\ High (precharge) Pulse duration, write Setup time, column address before CAS\ low Setup time, row address before RAS\ low Setup time, data 5 Setup time, read before CAS\ low Setup time, W\ low before CAS\ high Setup time, W\ low before RAS\ high Setup time, W\ low before CAS\ low (early-write operation only) Setup time, W\ High (CBR refresh only) Hold time, column address after CAS\ low Hold time, data after RAS\ low Hold time, data 5 Hold time, column address after CAS\ low Hold time, row address after RAS\ low Hold time, read after CAS\ High Hold time, read after RAS\ High Hold time, write after CAS\ low (early-write operation only) Hold time, write after RAS\ low Hold time, OE\ command Hold time, RAS\ referenced to OE\ Delay time, column address to W\ low (read-write operation only) Delay time, RAS\ low to CAS\ High (CBR refresh only) Delay time, CAS\ High to RAS\ low Delay time, RAS\ low to CAS\ High Delay time, CAS\ low to RAS\ low (CBR refresh only) Delay time, CAS\ low to W\ low (read-write operation only) 4 6 6 60 10 0 0 15 60 10 20 20 70 20 0 80 10 50 Hold time, W\ High (CBR refresh only) NOTES: 1. All cycle times assume tT = 5ns. 2. To assure tPC min, tASC should be > tCP. 3. In a read-write cycle, tRWD and tRWL must be observed. 4. In a read-write cycle, tCWD and tCWL must be observed. 5. Referenced to the later of CAS\ or W\ in write operations. 6. Either tRRH or tRCH must be satisfied for a read cycle. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 DRAM Austin Semiconductor, Inc. TIMING REQUIREMENTS (continued) SYM tRAD tRAL tCAL tRCD tRPC tRSH tRWD tCLZ tOED tREF tT PARAMETER Delay time, RAS\ low to column address 1 SMJ44400 -12 MAX 65 MIN 15 40 40 20 0 20 110 0 20 -8 MAX 40 MIN 20 50 50 -10 MAX 50 MIN 20 55 55 UNIT ns ns ns Delay time, column addresss to RAS\ High Delay time, column addresss to CAS\ High Delay time, RAS\ low to CAS\ low 1 60 25 0 25 135 0 25 75 25 0 30 160 0 30 90 ns ns ns ns ns ns Delay time, RAS\ High to CAS\ low Delay time, CAS\ low to RAS\ High Delay time, RAS\ low to W\ low (read-write operation only) CAS\ to output in low Z OE\ to data delay Refresh time interval Tranistion time 3 2 16 16 16 ms NOTES: 1. Maximum value specified only to assure access time. 2. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access times as the outputs are driven when CAS\ and OE\ are low. 3. Transition times (rise and fall) for RAS\ and CAS\ are to be a minimum of 3ns and a maximum of 50ns. PARAMETER MEASUREMENT INFORMATION Figure 1. Load Circuit for Timing Parameters 1.31V RL = 218 Output Under Test CL = 100 pF1 Output Under Test CL = 100 pF1 R2 = 295 5V R1 = 828 (a) LOAD CIRCUIT NOTES: 1. CL includes probe and fixture capacitance. (b) ALTERNATE LOAD CIRCUIT SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 DRAM Austin Semiconductor, Inc. READ-CYCLE TIMING SMJ44400 1 NOTES: 1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access tiems as the outputs are driven when CAS\ and OE\ are low. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 DRAM Austin Semiconductor, Inc. EARLY-WRITE-CYCLE TIMING SMJ44400 SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 DRAM Austin Semiconductor, Inc. WRITE-CYCLE TIMING SMJ44400 SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 DRAM Austin Semiconductor, Inc. READ-WRITE CYCLE TIMING SMJ44400 (1) NOTES: 1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access tiems as the outputs are driven when CAS\ and OE\ are low. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 DRAM Austin Semiconductor, Inc. SMJ44400 ENHANCED-PAGE-MODE READ-CYCLE TIMING (2) (2) (1) NOTES: 1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access tiems as the outputs are driven when CAS\ and OE\ are low. 2. Access time is tCPA or tAA dependent. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 DRAM Austin Semiconductor, Inc. SMJ44400 ENHANCED-PAGE-MODE WRITE-CYCLE TIMING2 (1) (1) NOTES: 1. Referenced to CAS\ or W\, whichever occurs last. 2. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 DRAM Austin Semiconductor, Inc. SMJ44400 ENHANCED-PAGE-MODE READ-WRITE-CYCLE TIMING2 (1) (1) NOTES: 1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access times as the outputs are driven when CAS\ and OE\ are low. 2. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 DRAM Austin Semiconductor, Inc. RAS\-ONLY REFRESH TIMING SMJ44400 SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 DRAM Austin Semiconductor, Inc. SMJ44400 AUTOMATIC-CBR-REFRESH-CYCLE TIMING SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 DRAM Austin Semiconductor, Inc. HIDDEN-REFRESH-CYCLE (READ) TIMING SMJ44400 (1) NOTES: 1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access times as the outputs are driven when CAS\ and OE\ are low. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 DRAM Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #113 (Package Designator JD) SMD 5962-90847, Case Outline U SMJ44400 D D1 A Q L E S1 Pin 1 b2 e b eA c SMD Specifications SYMBOL A b b2 c D D1 E eA e Q L S1 MIN --0.015 0.045 0.008 0.980 0.890 0.380 0.385 0.100 BSC 0.015 0.125 --0.060 0.200 0.070 MAX 0.175 0.021 0.065 0.014 1.030 0.910 0.410 0.420 NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 DRAM Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #308 (Package Designator HR) SMD 5962-90847, Case Outline X L E SMJ44400 Q A c SYMBOL A b c D E e L Q S SMD Specifications MIN MAX 0.080 0.100 0.015 0.021 0.004 0.010 0.690 0.710 0.483 0.497 0.050 TYP 0.340 0.370 0.025 0.035 0.101 0.133 NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 432 4321 4321 4321 4321 1 4321 4321 4321 432 4321 4321 4321 4321 4321 4321 1 4321 4321 4321 432 4321 4321 4321 4321 4321 4321 1 654321 4321 654321 e D b S DRAM Austin Semiconductor, Inc. SMJ44400 ORDERING INFORMATION EXAMPLE: SMJ44400-12JDM Device Number SMJ44400 SMJ44400 SMJ44400 Speed ns -80 -10 -12 Package Type JD JD JD Process /* /* /* EXAMPLE: SMJ44400-80HRM Device Number SMJ44400 SMJ44400 SMJ44400 Speed ns -80 -10 -12 Package Type HR HR HR Process /* /* /* *AVAILABLE PROCESSES M = Extended Temperature Range -55oC to +125oC SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 20 DRAM Austin Semiconductor, Inc. SMJ44400 ASI TO DSCC PART NUMBER CROSS REFERENCE* ASI Package Designator JD TI Part #** SMJ44400-12/JDM SMJ44400-10/JDM SMJ44400-80/JDM SMD Part # 5962-9084701MUA 5962-9084702MUA 5962-9084703MUA ASI Package Designator HR TI Part #** SMJ44400-12/HRM SMJ44400-10/HRM SMJ44400-80/HRM SMD Part # 5962-9084701MXA 5962-9084702MXA 5962-9084703MXA * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. ** Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999. SMJ44400 Rev. 2.0 10/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 21 |
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